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12 Inch Silicon Wafer FZ Intrinsic Undoped Orientation 100 Prime Grade 12"

XIAMEN POWERWAY ADVANCED MATERIAL CO., LTD.
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12 Inch Silicon Wafer FZ Intrinsic Undoped Orientation 100 Prime Grade 12"

Brand Name : PAM-XIAMEN

Place of Origin : China

MOQ : 1-10,000pcs

Price : By Case

Payment Terms : T/T

Supply Ability : 10,000 wafers/month

Delivery Time : 5-50 working days

product name : 12inch Silicon Wafer

brand : powerway

Dopant : Undoped

Conductance type : Intrinsic

other name : 12" Silicon wafer

size : 12"

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12 Inch Silicon Wafer FZ Intrinsic Undoped Orientation 100 Prime Grade 12"

Found in 1990,Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN) is a leading manufacturer of semicon doctor semiconductor material in China. PAM-XIAMEN develops advanced crystal growth and epitaxy technologies, manufacturing processes, engineered substrates and semiconductor devices. PAM-XIAMEN’s technologies enable higher performance and lower cost manufacturing of semiconductor wafer. For almost 30 years, PAM-XIAMEN aims to manufacture monocrystalline silicon wafer from the pulling process to get the ingot up to the final step which is the cleaning process, and vertically integrating to epi growth(silicon epi wafer) . This production and epi growth flow allows to maintain a reliable and qualitative consistency. Welcome you to enquire our engineer team, and we will give you full technology support.

12inch Silicon Wafer FZ Intrinsic Undoped Orientation 100 Prime Grade 12"

Type Conduction Type Orientation Diameter(mm) Resistivity(Ω•cm)
High resistance N&P <100>&<111> 50 - 300 >1000
NTD N <100>&<111> 50 - 300 30-800
CFZ N&P <100>&<111> 50 - 300 1-50
GD N&P <100>&<111> 50 - 300 0.001-300

Parameter Unit Value
Crystalline structure - Monocrystalline
Growth technique - FZ
Crystal Orientation - 100
Conductance type - Intrinsic
Dopant - Undoped
Diameter mm 300±0.2 mm
Resistivity Ω/cm2 8000-14000Ωcm
Thickness um 650±5µm
TTV um ≤15 um
BOW um ≤35 um
Warp um ≤35 um
Site Flatness SFQD um 20X20mm: 0.40um
Surface Metals (Al,Ca,Cu,Fe,Ni,Zn,Cr,Na) Atoms/cm2 Max 5E10/cm2
(G)STIR um Customer standard
Site Flatness-STIR um Customer standard
Metrology edge exclusion
(lpd’s, mechanical parameters)
mm 3
LPD's - LPDs >= 0,30 µm (including COP’s) <=25
LPDs >= 0,20 µm (including COP’s) <=30
LPDs >= 0,16 µm (including COP’s) <=60
Oxygen Concentration ppma 11-15 PPMA
Carbon Concentration ppma <1E16/cc
RRG - ≤15%
Front Surface - Polished
Back Surface - Polished
Edge Surface Condition SEMI STD or Customer Request
Notch - SEMI STD
Laser mark - SEMI STD or Customer Request
Packaging Packaged in a class 100 clean room environment,
Heat-sealed plastic inner/aluminium foil outer bags,
Vacuum Packing
If specific requirement by customer, will adjust accordingly
Parameter Unit Value

How is Silicon Wafer Made?

Growth of Silicon Ingot: single crystal silicon wafers grow via the Czochralski (CZ) and FZ method,CZ ingot growth requires chunks of virgin polycrystalline silicon, depending on the dopant, the ingot becomes a P or N type ingot (boron: P type; Phosphorus, antimony, arsenic: N type).

Slicing:Once the ingot is fully-grown, it is ground to a rough size diameter that is slightly larger than the target diameter of the final silicon wafer. The ingot has a notch or flat cut into it, the ingot proceeds to slicing. The diamond edge saw helps to minimize damage to the wafers, thickness variation, and bow and warp defects.

After the wafers have been sliced, the lapping process begins.

Cleaning:The final and most crucial step in the manufacturing process is polishing the wafer. This process takes place in a clean room. Clean rooms have a rating system that ranges from Class 1 to Class 10,000. These particles are not visible to the naked eye and in an uncontrolled atmosphere, the workers must wear clean room suits that cover their body from head to toe and do not collect or carry any particles.

Polishing:Most prime grade silicon wafers go through 2-3 stages of polishing, using progressively finer slurries or polishing compounds. The polishing process occurs in two steps, which are stock removal and final chemical mechanical polish (CMP). Both processes use polishing pads and polishing slurry. The stock removal process removes a very thin layer of silicon and is necessary to produce a wafer surface that is damage-free. After polishing, the silicon wafers proceed to a final cleaning stage that uses a long series of clean baths. This process removes surface particles, trace metals, and residues. Oftentimes a backside scrub is done to remove even the smallest particles.

Packaging:Once the wafers complete the final cleaning step, engineers sort them by specification and inspect them under high intensity lights or laser-scanning systems. This detects unwanted particles or other defects that may have occurred during fabrication. All wafers that meet the proper specifications are packaged in cassettes and sealed with tape. The wafers ship in a vacuum-sealed plastic bag with an airtight foil outer bag. This ensures that no particles or moisture enters the cassette upon leaving the clean room.

PAM-XIAMEN can offer you technology and wafer support, for more information, please visit our website: https://www.powerwaywafer.com,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Quality is our first priority. PAM-XIAMEN has been ISO9001:2008, owns and shares four modern facories which can provide quite a big range of qualified products to meet different needs of our customers, and every order has to be handled through our rigorous quality system. Test report is provided for each shipment, and each wafer are warranty.Before 1990, we are stated owned condensed matter physics research center. In 1990, center launched Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN), now it is a leading manufacturer of compound semiconductor material in China.


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